The present disclosure generally relates to chip design methods for semiconductor chips, and particularly to methods of identifying lithographic hot spots in a chip design layout and a system for implementing the same.
A chip design layout for a semiconductor chip includes multiple layout patterns having various levels of lithographic printability. Some layout patterns may be robust enough to be ported into another chip design layout employing a reduced minimum dimension. For example, some layout patterns for the 45 nm technology node may have a high level of printability to enable shrinking of the layout pattern for the 32 nm technology node without modification. However, some other layout patterns may exacerbate an existing printability problem if ported to a technology node employing a reduced minimum dimension. Particularly, a layout pattern that is known to have limited printability at one technology node would present severe printability problems if ported to another technology node employing a reduced minimum dimension.
A layout pattern attributed with limited printability at a technology node is referred to as a “lithographic hot spot” or “hot spot.” A hot spot potentially or factually causes printability problems or yield problems. Identification of hot spots and taking measures to overcome the adverse effects of the hot spots is a key procedure to ensure successful manufacturability and fabrication yield. Measures to overcome the adverse effects may be modification of the design layout and/or modification of lithographic processes to maximize the processing window at corresponding lithography steps.
Because scaling of dimensions typically aggravate printing problems for hot spots, the printability or yield problems seen in hot spots in a design layout in a technology node is repeated in the next technology node employing reduced dimensions. While identical layout patterns employing different minimum dimensions, i.e., direct “shrinks” of prior layout patterns, can be easily identified, most design layouts are modified from one generation to the next. Thus, knowledge gained by analysis of hot spots in one technology node is difficult to transfer to the next technology node.
Currently, the printability or yield problems are identified and fixed only within the same technology node. Further, predicting the printability potentially problematic patterns or structures becomes more difficult in the area of computational lithography due to the ever decreasing design scales, variability of design patterns, and the corresponding process variations. Thus, the information on the pattern of hot spots as generated in one technology node is difficult to transfer to the next technology node.